The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to power distribution for semiconductor memory devices.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can repeatedly write data into RAM and read data from RAM. This is in contrast to ROM (read-only memory), which generally only permits the user in routine operation to read data already stored on the ROM. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM generally cannot be written to in routine operation. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAMs can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
Many SDRAM devices are housed in packages that have an industry-standard pin layout and are of specified lengths and widths, such as a TSOP (thin, small-outline package) having a width of about 400 mils and a length dependent upon the number of pins. Memory chips in known TSOP memory packages have been oriented lengthwise within the package, as illustrated in FIG. 1A, and orthogonally within the package, as illustrated in FIG. 1B. FIGS. 1A and 1B depict industry-standard pin layouts for 44-pin SDRAM TSOP packages.
In the assembly depicted in FIG. 1A, memory chip 60 is oriented lengthwise within the package 62 with the major axis of the memory chip 60 extending substantially parallel to the major axis of the package 62. In the memory chip 60 of FIG. 1A, chip bond pads are located at opposite ends of the memory chip 60.
In the assembly depicted in FIG. 1B, memory chip 60 is oriented orthogonally within the package 62 with the major axis of the memory chip 60 extending substantially perpendicular to the major axis of the package 62. In the memory chip 60 of FIG. 1B, chip bond pads are located between the banks of memory arrays, or memory banks 64, located on memory chip 60.
For either assembly type, the chip bond pads correspond to interconnect pins of the package 62, such as address pins, data pins, clock and control signal pins, and power input pins. In general, there is a one-to-one relationship between the chip bond pads of a memory chip 60 and the interconnect pins of a package 62. However, certain interconnect pins may couple to more than one chip bond pad. The chip bond pads of the memory chip 60 are coupled to the interconnect pins of the package 62 in a conventional manner.
Integrated circuit chips, such as memory chips 60, are generally powered using a supply potential, such as VCC, and a ground potential, such as VSS. The industry-standard pin layouts for current SDRAM packages require power input pins for the ground potential VSS on a first side 74 of the package 62 and power input pins for the supply potential VCC on a second and opposite side 76 of the package 62. VCC power chip bond pads 66 are generally located on opposing ends of the memory chip 60 and are coupled to the VCC power input pins located near their corresponding end. For example, VCC power chip bond pads 66 located adjacent end 70 of the package 62 are coupled to the VCC power input pin located near end 70 while VSS power chip bond pads 68 located adjacent end 72 of the package 62 are coupled to the VSS power input pin located near end 72. To simplify the drawings, remaining chip bond pads, such as clock and control signal chip bond pads CLK, CKE, DQM, RAS#, CAS#, WE# and CS#, data chip bond pads DQ0-DQ7, address chip bond pads A0-A10 and BA, and DQ power input chip bond pads VCCQ and VSSQ, are not labeled in FIGS. 1A-1B.
As memory devices continue increasing in overall memory size and speed, power distribution becomes more critical especially as design rules continue to decrease. However, the industry-standard pin layouts restrict the ability of the designer to freely place power chip bond pads 66 and 68 around the memory chip as all VCC power input pins are on one side 76 of the package 62 while all VSS power input pins are on the opposite side 74 of the package 62.
Furthermore, to reduce undesirable parasitics, the VCC power chip bond pads 66 are usually coupled by a power connection internal to the memory chip 60. Likewise, the VSS power chip bond pads 68 are usually coupled by a second power connection internal to the memory chip 60. These power connections may take the form of a semiconductor die metalization layer. Such power connections use a significant amount of die real estate to connect these sources together properly, thus increasing costs and reducing production capacity. Furthermore, if the IR (inductance/resistance) drop along these power connections is too high, voltage drops or fluctuations may create undesirable signal characteristics within the integrated circuit. These concerns are magnified for those architectures having the memory device located between the power chip bond pads.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate architecture and assembly of semiconductor memory devices.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
The invention includes memory assemblies and their components adapted for memory chips having chip bond pads interposed between a memory device and each side of the memory chip. Embodiments include memory chips having power input chip bond pads for receiving a power input, with at least one of the power input chip bond pads located in each of at least three quadrants of the memory chip. Further embodiments include lead-over-chip leadframes and memory assemblies for coupling a single memory package interconnect pin to chip bond pads located on both sides of the memory chip, regardless of the location of the interconnect pin. Embodiments include memory chips in memory assemblies having chip bond pads on both sides of the memory chip shorted to each other by a single lead of a lead-over-chip leadframe.
For one embodiment, the invention provides a memory chip. The memory chip includes a substrate having four quadrants, a memory device fabricated on the substrate, and a plurality of first power input chip bond pads for receiving a first power input. The plurality of first power input chip bond pads are fabricated on the substrate and are coupled to the memory device. At least one of the first power input chip bond pads is located in each of at least three of the quadrants of the substrate. For another embodiment, the memory device contained in the memory chip is a synchronous flash memory device having an array of non-volatile flash memory cells and a command execution logic for receiving at least a system clock input signal and for generating commands to control operations performed on the array of non-volatile flash memory cells, wherein the commands are synchronized to the system clock input signal.
For a further embodiment, the invention provides a memory chip. The memory chip includes a substrate having a first side substantially parallel to a major axis of the memory chip and having two ends and a center, a second side substantially parallel to the major axis and having two ends and a center, and four corners. A corner is located at each end of the first and second sides. The memory chip further includes a memory device fabricated on the substrate. The memory chip still further includes at least five first power input chip bond pads for coupling the memory device to a supply potential. At least one first power input chip bond pad is located near each of three corners, at least one first power input chip bond pad is located near the center of the first side, and at least one first power input chip bond pad is located near the center of the second side. The memory chip still further includes at least five second power input chip bond pads for coupling the memory device to a ground potential. At least one second power input chip bond pad is located near each of three corners, at least one second power input chip bond pad is located near the center of the first side, and at least one second power input chip bond pad is located near the center of the second side.
For a further embodiment, the invention provides a lead-over-chip leadframe for a memory package having a pin layout substantially similar to an industry-standard SDRAM pin layout. The leadframe includes a first side, a second side opposite the first side, and a centerline between the first and second sides. At least one lead originating from the first side of the leadframe has terminations on each side of the centerline.
The invention further provides memory chips, leadframes and assemblies of various scope.